Influence of Annealing Conditions on the Bias Temperature Stability of MgZnO Thin Film Transistors

Abstract

We report the experimental results regarding the stability of back-channel cut bottom gate thin film transistors (TFTs) with Mg0.05Zn0.95O active layers. The TFTs are all fabricated at room temperature. Two different thermal annealing conditions are applied to the devices, 200 oC for 5 hours and 350 oC for half an hour. In both annealing conditions, the devices show similar electric characteristics initially. Nevertheless, 350 oC annealed TFTs show much better stability under gate bias stressing. When gate-bias stressing is applied to TFTs at 80 oC, the transfer curves exhibit much more significant humps at subthreshold regimes for 200 oC annealed TFTs compared to 350 oC annealed TFTs. It is highly suspected that the humps may be due to the two phase nature of as-sputtered MgZnO thin film. 350 oC annealing may transform the two phase mixture into single phase, leading to more stable TFTs.