Architectural Design Issues in a Clockless 32 Bit Processor Using an Asynchronous HDL
Author:
Publisher
Wiley
Subject
Electrical and Electronic Engineering,General Computer Science,Electronic, Optical and Magnetic Materials
Reference10 articles.
1. Applications of asynchronous circuits
2. Designing asynchronous standby circuits for a low-power pager
3. ARM996HS: The First Licensable, Clockless 32-Bit Processor Core
4. Three generations of asynchronous microprocessors
5. Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems;ETRI Journal;2017-08
2. Design of a clockless MSP430 core using mixed asynchronous design flow;IEICE Electronics Express;2017
3. Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains;JSTS:Journal of Semiconductor Technology and Science;2015-04-30
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