Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems-Reference-Cited by-同舟云学术

登录注册会员服务联系我们

Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems

Published:2017-08 Issue:4 Volume:39 Page:582-591
ISSN:1225-6463
Container-title:ETRI Journal
language:en
Short-container-title:ETRI Journal

Author:

Oh Myeong-Hoon,Kim Young Woo,Kim Hag Young,Kim Young-Kyun,Kim Jin-Sung

Funder

Korea government(MSIT)

Publisher

Wiley

Subject

Electrical and Electronic Engineering,General Computer Science,Electronic, Optical and Magnetic Materials

Link

http://onlinelibrary.wiley.com/wol1/doi/10.4218/etrij.17.0116.0052/fullpdf

Reference17 articles.

1. Architectural Design Issues on a Clockless 32-bit Processor Using an Asynchronous HDL;Oh;ETRI J.,2013

2. Principles of Asynchronous Circuit Design

3. Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication;McLaughlin;IEEE Trans. VLSI Syst.,2009

4. Efficient Self-Timing with Level-Encoded 2-Phase Dual-Rail (LEDR);Dean;Proc. Univ, California/Santa Cruz Conf. Adv. Res. VLSI,1991

5. Exploiting New Interconnect Technologies in On-chip Communication;Kim;IEEE J. Emerg. Select. Topics Circuits Syst.,2012

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity;International Journal of Electronics and Telecommunications;2023-07-26

2. Signal integrity analysis of system interconnection module of high‐density server supporting serial RapidIO;ETRI Journal;2019-04-29

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370

www.globalauthorid.com

TOP