Affiliation:
1. Sree Vidyanikethan Engineering College
Abstract
Every digital signal processing application performs multiplication operations. The addition and shift operations are part of multiplication operation. Many ideas have been created for computing systems with different design goals in terms of power, area, and speed. Typical architecture of these applications include digital signal processor (DSP), fast Fourier transform (FFT), and Multiply and Accumulate (MAC) unit. This paper offers a new way to increase the speed of DSP systems. This method uses four 2x2 LUT (look-up table) multipliers to demonstrate it at a 4x4 multiplier. The proposed multiplier was created using the Xilinx Vivado software and programmed in the Verilog HDL language. In addition, the delay, area, and power consumption of the proposed multiplier design differ from those of conventional multipliers. The simulation results show that, compared to typical methods, the operation consumes less power, reaching only 3.751 W compared to the conventional multiplier of 4.804 W, and shows lower latency.
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