Affiliation:
1. YMCA University of Science and Technology
Abstract
In this paper, the basic D flip-flop has been considered with TSPC (True Single-Phase Clock) logic. Here, the leakage power of 1031 pW fell to the power for the operation of the memory elements, which is a lot compared to other triggers. The challenge is to reduce the optimal power off to conserve idle power. To solve this problem, three different powersaving techniques were considered, such as Technique 1: sleeping transistors, Technique 2: sleepy stack, and Technique 3: sleepy keeper. In a comparative study, it was observed that Technique 1 is the most optimal method for delays (falling and rising) and off-state leakage power compared to the other methods considered. The off-state leakage power was 1.753 pW, which is 93.07% and 76.90% less than by Techniques 2 and 3, respectively.
Reference19 articles.
1. A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems
2. Asthana, A., & Akashe, S. (2013). Power efficient d flip
flop circuit using MTCMOS technique in deep submicron
technology. International Journal of Engineering
Research & Technology, 2(11), 1785-1791.
3. Low-power CMOS digital design
4. Deepthi, K., & Srikanth, M. P. (2019). Design of 18-
transistor TSPC Flip-Flop based on logic structure reduction
schemes. International Journal of Research, 8(5), 1049-1056.
5. Design of Low Power Adaptive Pulse TriggeredFlip-Flop Using Modified Clock Gating Schemeat 90nm Technology