A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
Author:
Publisher
Zhejiang University Press
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1631/FITEE.1900653.pdf
Reference31 articles.
1. Berny AD, Niknejad AM, Meyer RG, 2005. A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration. IEEE J Sol-State Circ, 40(4):909–917. https://doi.org/10.1109/JSSC.2004.842851
2. Chang HH, Wang PY, Zhan JHC, et al., 2008. A fractional spur-free ADPLL with loop-gain calibration and phase-noise cancellation for GSM/GPRS/EDGE. IEEE Int Conf on Solid-State Circuits, p.200–201, 606. https://doi.org/10.1109/ISSCC.2008.4523126
3. Chang WS, Huang PC, Lee TC, 2014. A fractional-N divider-less phase-locked loop with a subsampling phase detector. IEEE J Sol-State Circ, 49(12):2964–2975. https://doi.org/10.1109/JSSC.2014.2359670
4. Chiu WH, Chang TS, Lin TH, 2009. A charge pump current missmatch calibration technique for ΔΣ fractional-N PLLs in 0.18-µm CMOS. IEEE Asian Solid-State Circuits Conf, p.73–76. https://doi.org/10.1109/ASSCC.2009.5357182
5. de Muer B, Steyaert MSJ, 2002. A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800. IEEE J Sol-State Circ, 37(7):835–844. https://doi.org/10.1109/JSSC.2002.1015680
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