Multi-Core Cache Hierarchies

Author:

Balasubramonian Rajeev,Jouppi Norman P.,Muralimanohar Naveen

Publisher

Morgan & Claypool Publishers LLC

Subject

Hardware and Architecture

Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A High-Performance, Energy-Efficient Modular DMA Engine Architecture;IEEE Transactions on Computers;2024-01

2. MAPCP: Memory Access Pattern Classifying Prefetcher;The International Symposium on Memory Systems;2021-09-27

3. Reused-Based Replacement Policy for Last-Level Cache with Minimum Hardware Cost;Emerging Technologies for Smart Cities;2021

4. A Survey on the Software and Hardware-Based Influences on the Worst-Case Execution Time;Advances on P2P, Parallel, Grid, Cloud and Internet Computing;2020-10-09

5. Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors;2020 IEEE 38th International Conference on Computer Design (ICCD);2020-10

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