1. Brainard [Advanced Processes for 193-nm Immersion Lithography];Yayi,2009
2. Utilization of spin-on and reactive ion etch critical dimension shrink with double patterning for 32 nm and beyond contact level interconnects,;Karen,2009
3. Spacer double patterning technique for sub-40nm DRAM manufacturing process development,;Weicheng,2008
4. Novel approaches to implement the self-aligned spacer double-patterning process toward 11-nm node and beyond;Hidetami,2011
5. Wet trimming process for critical dimension reduction;Sun,2008