Immersion resist process for 32-nm node logic devices-Reference-Cited by-同舟云学术

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Immersion resist process for 32-nm node logic devices

Published:2008-03-14 Issue: Volume: Page:
ISSN:0277-786X
Container-title:Advances in Resist Materials and Processing Technology XXV
language:
Short-container-title:

Author:

Ema Tatsuhiko,Sho Koutaro,Yonemitsu Hiroki,Seino Yuriko,Fujise Hiroharu,Yamada Akiko,Mimotogi Shoji,Kitamura Yosuke,Nagai Satoshi,Fujii Kotaro,Fukushima Takashi,Komukai Toshiaki,Nomachi Akiko,Azuma Tsukasa,Ito Shinichi

Publisher

SPIE

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Development of spin-on metal hardmask (SOMHM) for advanced node;Advances in Patterning Materials and Processes XXXII;2015-03-20

2. Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool;Advances in Resist Materials and Processing Technology XXVI;2009-03-13

3. Practical requirement for reflectivity control in sub 30nm device using high NA immersion lithography;SPIE Proceedings;2008-11-20

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