1. Design and pitch scaling for affordable node transition and EUV insertion scenario;Kim,2017
2. Low-track height standard-cell design in N5 using scaling boosters;Sherazi,2017
3. Patterning Control Strategies for Minimum Edge Placement Error in Logic Devices;Mulkens,2017
4. SAQP and EUV block patterning of BEOL metal layers on IMEC’s iN7 platform;Bekaert,2017
5. Single exposure EUV patterning of BEOL metal layers on the Imec iN7 platform;Blanco Carballo,2017