Design for nanoimprint lithography: hot spot modification through total NIL process simulation

Author:

Kobayashi Sachiko,Yamashita Kyoji,Tsuda Hirotaka,Washida Kazuhiro,Komori Motofumi,Im Ji-Young,Kono Takuya,Nakasugi Tetsuro

Publisher

SPIE

Reference15 articles.

1. Nanoimprint lithography and future patterning for semiconductor devices

2. Sub-100 nm pattern formation by roll-to-roll nanoimprint;Inanami,2012

3. Sub-30 nm pattern formation by roll-to-roll nanoimprint lithography;Inanami,2012

4. Controlling and thinning of residual layer thickness in roll-to-roll nanoimprint technology;Inanami,2013

5. NIL defect performance toward high volume mass production;Hatano,2016

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1. NIL solutions using computational lithography for semiconductor device manufacturing;DTCO and Computational Patterning III;2024-04-10

2. Design process integration enabling the productivity enhancement for nanoimprint lithography;DTCO and Computational Patterning;2022-05-26

3. Improvement of productivity by spin-coating and flash imprint lithography;Journal of Micro/Nanopatterning, Materials, and Metrology;2022-03-04

4. Enabling nanoimprint simulator for quality verification: process-design co-optimization toward high-volume manufacturing;Journal of Micro/Nanopatterning, Materials, and Metrology;2022-01-04

5. Enabling nanoimprint simulator for quality verification; Process-design co-optimization toward high volume manufacturing;Design-Process-Technology Co-optimization for Manufacturability XIV;2020-03-23

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