Automated hot-spot fixing system applied to the metal layers of 65-nm logic devices

Author:

Kobayashi Sachiko

Publisher

SPIE-Intl Soc Optical Eng

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference10 articles.

1. Layout optimization at the pinnacle of optical lithography

2. Integrating DfM components into a cohesive design-to-silicon solution (Invited Paper)

3. Yield-enhanced layout generation by new design for manufacturability (DfM) flow

4. S. Inoue , “Patterning friendly design methodology for 65 nm and beyond technology nodes,”8th Int. Forum Semiconductor Technol.(June 2005).

5. S. Inoue, T. Kotani, S. Nojima, S. Tanaka, K. Hashimoto, and I. Mori , “Total hot spot management from design rule definition to silicon fabrication,”Electron. Design Processes Workshop, Moneterey, Calif. (April 2003).

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1. Optical Lithography;Nanofabrication;2024

2. Analysis and Optimization of Defect Generation Due to Mechanical Stress in High-Density SRAM;IEEE Journal of the Electron Devices Society;2021

3. Nanofabrication by Photons;Nanofabrication;2016-08-11

4. Hotspot fixing using ILT;SPIE Proceedings;2011-03-17

5. Score-based fixing guidance generation with accurate hot-spot detection method;SPIE Proceedings;2009-03-13

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