Method of glitch reduction in DAC with weight redundancy-Reference-Cited by-同舟云学术

Method of glitch reduction in DAC with weight redundancy

Published:2015-12-18 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
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Author:

Azarov Olexiy D.,Murashchenko Olexander G.,Chernyak Olexander I.,Smolarz Andrzej,Kashaganova Gulzhan

Publisher

SPIE

Reference9 articles.

1. Direct Digital Synthesis (DDS) Controls Waveforms in Test Measurement and Communications;Murphy,2005

2. A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC’s;Catteau,2007

3. A novel dynamic calibration approach for current-steering DACs;Su,2005

4. Azarov, O.D., [Analogue-to-digital digit-by-digit conversion on the base of calculation system with weight redundancy–Monograph] Vinnytsia, VNTU, 232 (2010).

5. A low-glitch and small-logic-area Fibonacci Series DAC;Hokazono,2011

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