1. A 14 nm logic technology featuring 2nd-generation fin-FETs, air-gapped interconnects, selfaligned double patterning and a 0.0588 µm2 SRAM cell size;Natarajan,2014
2. Considerations for Ultimate CMOS Scaling
3. Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Si Substrates;Mertens,2016
4. Contactless electrical testing of large area specimens using electron beams
5. New Voltage Contrast Imaging Method for Detection of Electrical Failures;Nozoe,2000