1. Low k1 logic design using gridded design rules;Smayling,2008
2. Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond;Liebmann,2009
3. Apf pitch-halving for 22nm logic cells using gridded design rules;Smayling,2008
4. Gridded design rule scaling: taking the cpu toward the 16nm node;Bencher,2009
5. 22nm half-pitch patterning by cvd spacer self alignment double patterning (sadp);Bencher,2008