Architectural strategies in standard-cell design for the 7 nm and beyond technology node-Reference-Cited by-同舟云学术

Architectural strategies in standard-cell design for the 7 nm and beyond technology node

Published:2016-02-25 Issue:1 Volume:15 Page:013507
ISSN:1932-5150
Container-title:Journal of Micro/Nanolithography, MEMS, and MOEMS
language:en
Short-container-title:J. Micro/Nanolith. MEMS MOEMS

Author:

Sherazi Syed Muhammad Yasser¹,Chava Bharani²,Debacker Peter²,Bardon Marie Garcia²,Schuddinck Pieter²,Firouzi Farshad²,Raghavan Praveen²,Mercha Abdelkarim²,Verkest Diederik²,Ryckaert Julien²

Affiliation:

1. KU Leuven, Department of Electrical Engineering, ESAT, Kasteelpark Arenberg 10, Leuven 3001, BelgiumbInteruniversitair Micro Elektronica Centrum, Department of Logic Technologies, Kapeldreef 75, Heverlee 3001, Belgium

2. Interuniversitair Micro Elektronica Centrum, Department of Logic Technologies, Kapeldreef 75, Heverlee 3001, Belgium

Publisher

SPIE-Intl Soc Optical Eng

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference25 articles.

1. FinFET basic cells evaluation for regular layouts

2. Tall FIN formation for FINFET devices of 20nm and beyond using multi-cycles of passivation and etch processes

3. Gate double patterning strategies for 10-nm node FinFET devices

4. A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation method

5. Optimizing standard cell design for quality

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