Simulation investigation of enabling technologies for EUV single exposure of Via patterns in 3nm logic technology-Reference-Cited by-同舟云学术

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Simulation investigation of enabling technologies for EUV single exposure of Via patterns in 3nm logic technology

Published:2020-04-02 Issue: Volume: Page:
ISSN:
Container-title:Extreme Ultraviolet (EUV) Lithography XI
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Author:

Gao Weimin,Chiou Tsann-Bim,Tseng Shih En,Woltgens Pieter,McManus Moyra K.,Seong Nakgeuon,Yen Anthony

Publisher

SPIE

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Evolution of Single-Molecule Electronic Interfaces;Langmuir;2024-01-16

2. ASAP5: A predictive PDK for the 5 nm node;Microelectronics Journal;2022-08

3. Computational lithographic study of 0.55 NA EUV single patterning for metal layers for the 2nm logic node and beyond;DTCO and Computational Patterning;2022-05-26

4. Attenuated phase shift masks: a wild card resolution enhancement for extreme ultraviolet lithography?;Journal of Micro/Nanopatterning, Materials, and Metrology;2022-05-11

5. iN5 EUV single expose patterning evaluation for via layers;International Conference on Extreme Ultraviolet Lithography 2021;2021-10-12

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