Spacer defined double patterning for sub-72 nm pitch logic technology-Reference-Cited by-同舟云学术

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Spacer defined double patterning for sub-72 nm pitch logic technology

Published:2010-03-11 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
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Author:

Kim Ryoung-Han,Mclellan Erin,Yin Yunpeng,Arnold John,Kanakasabapathy Sivananda,Mehta Sanjay,Ma Yuansheng,Burkhardt Martin,Cain Jason,McIntyre Greg,Colburn Matthew E.,Levinson Harry J.

Publisher

SPIE

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Wafer level critical dimension control in spacer-defined double patterning for sub-72 nm pitch logic technology;Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena;2012-03

2. Decomposition-aware standard cell design flows to enable double-patterning technology;SPIE Proceedings;2011-03-17

3. Spacer-defined double patterning for 20nm and beyond logic BEOL technology;SPIE Proceedings;2011-03-17

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