Considerations for pattern placement error correction toward 5nm node-Reference-Cited by-同舟云学术

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Considerations for pattern placement error correction toward 5nm node

Published:2017-03-27 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
language:
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Author:

Yaegashi Hidetami¹,Oyama Kenichi¹,Hara Arisa¹,Natori Sakurako¹,Yamauchi Shohei¹,Yamato Masatoshi¹,Koike Kyohei¹,Maslow Mark John²,Timoshkov Vadim²,Kiers Ton²,Di Lorenzo Paolo³,Fonseca Carlos⁴

Affiliation:

1. Tokyo Electron Ltd. (Japan)

2. ASML Netherlands B.V. (Netherlands)

3. IMEC (Belgium)

4. Tokyo Electron America, Inc. (United States)

Publisher

SPIE

Reference4 articles.

1. Low k1 logic design using gridded design rules;Smayling,2008

2. Extended scalability with self-aligned multiple patterning;Oyama,2013

3. EUV resist curing technique for LWR reduction and etch selectivity enhancement;Narishige,2012

4. CD bias control on hole pattern;Koike,2016

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Metal infiltration into chemically amplified resists to improve pattern fidelity;Advances in Patterning Materials and Processes XLI;2024-04-09

2. Standard wafer with programed defects to evaluate the pattern inspection tools for 300-mm wafer fabrication for 7-nm node and beyond;Journal of Micro/Nanolithography, MEMS, and MOEMS;2019-06-19

3. Characterizing interlayer edge placement with SEM contours;Journal of Micro/Nanolithography, MEMS, and MOEMS;2019-04-15

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