1. Phase edge lithography for sub 0.1 mu m electrical channel length in a 200 MM full CMOS process;Agnello,1995
2. Layout optimization at the pinnacle of optical lithography
3. Design implications of extremely restricted patterning
4. Bridging the resolution gap in 14 nm: designing for efficient transition to EUV (Invited Paper);Liebmann,2012
5. Innovations in Special Constructs for Standard Cell Libraries in Sub 28nm Technologies;Rashed,2013