Gate double patterning strategies for 10-nm node FinFET devices-Reference-Cited by-同舟云学术

Gate double patterning strategies for 10-nm node FinFET devices

Published:2015-03-05 Issue:1 Volume:14 Page:014504
ISSN:1932-5150
Container-title:Journal of Micro/Nanolithography, MEMS, and MOEMS
language:en
Short-container-title:J. Micro/Nanolith. MEMS MOEMS

Author:

Hody Hubert¹,Paraschiv Vasile²,Hellin David³,Vandeweyer Tom¹,Boccardi Guillaume¹,Xu Kaidong¹

Affiliation:

1. IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

2. SC Etch Tech Solutions, Strada Oancea 3, Iasi, Romania

3. Lam Research Corp., Kapeldreef 75, 3001 Leuven, Belgium

Publisher

SPIE-Intl Soc Optical Eng

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference8 articles.

1. Double patterning with dual hard mask for 28-nm node devices and below

2. Gate line width roughness control for advanced logic technologies;Meng,2012

3. Plasma-polymer interactions: A review of progress in understanding polymer resist mask durability during plasma etching for nanoscale fabrication

4. Blind separation of human- and horse-footstep signatures using independent component analysis

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