Performance of stacked nanosheet gate all around FET’s with EUV patterned gate and sheets-Reference-Cited by-同舟云学术

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Performance of stacked nanosheet gate all around FET’s with EUV patterned gate and sheets

Published:2021-02-22 Issue: Volume: Page:
ISSN:
Container-title:Extreme Ultraviolet (EUV) Lithography XII
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Author:

Seshadri Indira,Church Jennifer,Hundekar Prateek,Breton Mary,Zhang Jingyun,Miller Eric,Greene Andrew,Frougier Julien,Waskiewicz Chris,Li Tao,Kang Tsung-Sheng,Dechene Daniel,Radens Carl,Sieg Stuart,Basker Veeraraghavan,Felix Nelson,Mack Chris A.

Publisher

SPIE

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. EUV patterned gate variation reduction in next generation transistor architectures;Optical and EUV Nanolithography XXXVII;2024-04-10

2. Review of nanosheet metrology opportunities for technology readiness;Journal of Micro/Nanopatterning, Materials, and Metrology;2022-04-18

3. Device Characterization of Nanoscale Vertical-Channel Transistors Implemented with a Mesa-Shaped SiO2 Spacer and an In–Ga–Zn–O Active Channel;ACS Applied Electronic Materials;2021-08-31

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