Standard cell design in N7: EUV vs. immersion-Reference-Cited by-同舟云学术

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Standard cell design in N7: EUV vs. immersion

Published:2015-03-18 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
language:
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Author:

Chava Bharani,Rio David,Sherazi Yasser,Trivkovic Darko,Gillijns Werner,Debacker Peter,Raghavan Praveen,Elsaid Ahmad,Dusa Mircea,Mercha Abdelkarim,Ryckaert Julien,Verkest Diederik

Publisher

SPIE

Reference2 articles.

1. Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM;Vandewalle,2014

2. Rethinking ASIC design with next generation lithography and process integration;Vaidyanathan,2013

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2. Gate mapping impact on variability robustness in FinFET technology;Microelectronics Reliability;2019-09

3. Analysis of multi-e-beam lithography for cutting layers at 7-nm node;Journal of Micro/Nanolithography, MEMS, and MOEMS;2016-10-14

4. ASAP7: A 7-nm finFET predictive process design kit;Microelectronics Journal;2016-07

5. An integrated design-to-manufacturing flow for SADP;SPIE Proceedings;2016-03-16

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