Novel multi-bit parallel pipeline-circuit design for STT-MRAM

Abstract

In the paper, novel multi-bit parallel pipeline circuit design of STT-MRAM is proposed to improve the read and write efficiency. The shift register is utilized to change the series data into the parallel ones. Combined with the corresponding sense amplifier (SA) circuit and the write drive circuit, 4-bit data can be read or written in parallel in single cycle. With the 32 Kbit data test, the efficiencies of the read and the write operations of the proposed pipeline circuit are increased by 72.3% and 74.4%, separately, with the comparison of the incumbent series operations. The proposed strategy has potential application in the embedded high speed STT-MRAM.