1. Frontiers of silicon-on-insulator
2. Bonded planar double-metal-gate NMOS transistors down to 10 nm
3. D. Esseni, M. Mastrapasqua, C. Fiegna, G. K. Celler, L. Selmi, and E. Sangiorgie,IEDM’2001 Technical Digest(IEEE, Piscataway, NJ, 2001), p. 445.
4. D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda,IEDM’1989 Technical Digest(IEEE, Piscataway, NJ, 1989), p. 833.
5. X. Huang, W.C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.K. Choi, K. Asano, V. Subramanian, T.J. King, J. Bokor, and C. Hu,IEDM’1999 Technical Digest(IEEE, Piscataway, NJ, 1999), p. 67.