On the validity and applicability of models of negative capacitance and implications for MOS applications
Author:
Affiliation:
1. Advanced Logic Lab, Samsung Semiconductor, Inc., Austin, Texas 78754, USA
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
http://aip.scitation.org/doi/pdf/10.1063/1.5036984
Reference29 articles.
1. Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
2. A. I. Khan , C. W. Yeung , C. Hu , and S. Salahuddin , in IEEE IEDM Technical Digest (2011), pp. 11.3.1–11.3.4.
3. Experimental confirmation of temperature dependent negative capacitance in ferroelectric field effect transistor
4. Stability Constraints Define the Minimum Subthreshold Swing of a Negative Capacitance Field-Effect Transistor
5. Experimental observation of voltage amplification using negative capacitance for sub-60 mV/decade CMOS devices
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