Conformal bilayer h-AlN epitaxy on WS2 by ALD with ultralow leakage current

Author:

Wang Shin-Yuan1ORCID,Chang Shu-Jui2ORCID,Huang Yu-Che3,Chih Jia Hao1,Lin Yu-Chin1,Cheng Chao-Ching2ORCID,Radu Iuliana2ORCID,Hu Chenming34ORCID,Chien Chao-Hsin1ORCID

Affiliation:

1. Department of Electronics Engineering, National Yang Ming Chiao Tung University 1 , Hsinchu 30010, Taiwan

2. Corporate Research, Taiwan Semiconductor Manufacturing Company (TSMC) 2 , Hsinchu 30078, Taiwan

3. International College of Semiconductor Technology, National Yang Ming Chiao Tung University 3 , Hsinchu 30010, Taiwan

4. Department of Electrical Engineering and Computer Sciences, University of California 4 , Berkeley, California 94720, USA

Abstract

In this work, we develop an ultrathin epitaxial h-AlN as an interfacial layer (IL) between HfO2 and monolayer WS2 channel by atomic layer deposition (ALD). The growth of ultrathin dielectrics using ALD has been challenging due to the dangling-bond-free surface of 2D materials. By utilizing sub-1 nm h-AlN as an IL and depositing HfO2 high-k dielectric, we were able to form a uniform and atomically flat gate dielectric without voids. The resulting structure exhibits an equivalent oxide thickness as low as 1 nm and ultra-low leakage currents of ∼10−6 A/cm2. The fabricated top-gate WS2 transistors demonstrate on-off ratios of around 106 and subthreshold swing as low as 93 mV/dec. Furthermore, we have verified the feasibility of using h-AlN IL for a gate-all-around structure. Our work presents a CMOS-compatible low-temperature ALD process for integrating gate dielectrics, offering excellent thickness scalability and uniform coverage around monolayer WS2 nanosheets. The combination of high-quality two-dimensional dielectrics and semiconductors will contribute to the development of future high-performance and low-power electronic devices.

Funder

Ministry of Science and Technology, Taiwan

Ministry of Education

Publisher

AIP Publishing

Subject

Physics and Astronomy (miscellaneous)

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