Effect of source–drain contact and channel length on the performance of vertical thin-film transistors

Abstract

Vertical thin-film transistors (V-TFTs) with an InSnO-stabilized ZnO channel were fabricated. The vertical architecture enables devices with submicron channel lengths (≤500 nm) to afford delivering drain current greatly exceeding that of conventional planar TFTs. Due to the submicron length of the V-TFT channel, an on/off state current higher than 107 can be achieved even with a drain voltage of 0.01 V, and the subthreshold swing was kept in the tens of mV/dec range owing to the efficacious device preparation. In order to understand the influence of structures on the device performance, the source–drain (S/D) contact and the channel length of V-TFTs were designed and studied. The results show that the increase in the contact area between the active layer and the S/D region can reduce the S/D contact resistance, thus affecting the drain current across the threshold region. When the channel length is shortened to a deep submicron size, the electrostatic coupling between the source and drain electrodes will lead to a decrease in the S/D barrier. This leads to the leakage-induced barrier reduction effect of V-TFTs.