Author:
Savarimuthu Sabeenian Royappan,Muthuraji Kalaiselvi Cinnu,Eswaran Paramasivam Muthan
Reference22 articles.
1. A. Deepa and C. Marimuthu, “High speed vlsi architecture for squaring binary numbers using yavadunam sutra and bit reduction technique,” International Journal of Applied Engineering Research 13, 4471–4474 (2018).
2. Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra
3. Performance Evaluation of Squaring Operation by Vedic Mathematics
4. R. B. Gowda, R. Banakar, et al., “Performance analysis of vedic multiplier with different square root bk adders,” in Emerging Research in Computing, Information, Communication and Applications (Springer, 2019) pp. 273–285.
5. Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters