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Springer Science and Business Media LLC
Reference21 articles.
1. Akanksha K and Shobha S 2015 Applications of Vedic multiplier designs-a review. In: Proceedings of the 4th international conference on reliability, infocom technologies and optimization (trends and future directions). pp. 1–6
2. Deepa A and Marimuthu C N 2017 A high speed VLSI architecture of a pipelined reed solomon encoder for data storage in communication systems. Asian J. Res. Soc. Sci. Hum. 7(2): 228–238
3. Neeraj M and Asmita H 2013 An advancement in the N*N multiplier architecture realization via the ancient Indian Vedic mathematics. Int. J. Electron. Commun. Comput. Eng. 4(2): 544–548
4. Jinesh S, Ramesh P and Thomas J 2015 Implementation of 64 bit high speed multipliers for DSP application-based on vedic mathematics. In: Proceedings TENCON 2015 IEEE region 10 conference. pp. 1–5
5. Arushi S, Dheeraj J, Sanjay J, Kumkum V and Swati K 2012 Compare Vedic multipliers with conventional hierarchical array of array multiplier. Int. J. Comput. Technol. Electron. Eng. 2(6): 52–55
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