1. L. Liu, V. Saripalli, V. Narayanan, and S. Datta, Proceeding of Electron Devices Meeting (IEDM), (IEEE International, 2011), pp. 4–51–45–4.
2. S. Kasai, M. Yumoto, and H. Hasegawa, Proceeding of Semiconductor Device Research Symposium, (IEEE International, 2001), pp. 622–625.
3. S. Eachempati, V. Sarapalli, V. Narayanan, and S. Datta, Proceeding of Symposium on Nanoscale Architectures (NANOARCH), (IEEE/ACM International, 2008), pp. 61–67.
4. Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network
5. Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits