Linear and symmetric synaptic weight update characteristics in van der Waals heterostructure transistors based on 2D In4/3P2Se6 barrier layer
Author:
Affiliation:
1. School of Physics, Henan Key Laboratory of Photovoltaic Materials, Henan Normal University 1 , Xinxiang, Henan 453007, China
2. School of Electronic Engineering, Chaohu University 2 , Hefei 238000, China
Abstract
Funder
training program for the national foundation of henan normal university
Scientific research star-up foundation for PhD of chaohu university
Natural Science Foundation of Henan Province
Natural Science Foundation of China
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
https://pubs.aip.org/aip/apl/article-pdf/doi/10.1063/5.0166462/18150559/141902_1_5.0166462.pdf
Reference56 articles.
1. Evolution of Bio‐Inspired Artificial Synapses: Materials, Structures, and Mechanisms
2. Room-temperature valley transistors for low-power neuromorphic computing
3. Controlled Optoelectronic Response in van der Waals Heterostructures for In‐Sensor Computing
4. Multifunctional Half-Floating-Gate Field-Effect Transistor Based on MoS2–BN–Graphene van der Waals Heterostructures
5. Van der Waals engineering of ferroelectric heterostructures for long-retention memory
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