Simultaneous flattening of Si(110), (111), and (001) surfaces for three-dimensional Si nanowires
Author:
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
http://aip.scitation.org/doi/pdf/10.1063/1.4731789
Reference15 articles.
1. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling
2. Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-к/metal-gate: Effects of hydrogen thermal annealing and nanowire shape
3. Short-channel effects in SOI MOSFETs
4. Ideal hydrogen termination of the Si (111) surface
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1. A Study on Substrate Orientation Dependence of Si Surface Flattening Process by Sacrificial Oxidation and Its Effect on MIS Diode Characteristics;IEICE Transactions on Electronics;2016
2. A Study on Si(100) Surface Flattening Utilizing Sacrificial Oxidation Process and Its Effect on MIS Diode Characteristics;IEICE Transactions on Electronics;2015
3. Atomically flat planarization of Ge(100), (110), and (111) surfaces in H2annealing;Applied Physics Express;2014-04-09
4. Development of Silicon Nanowire MOSFETs through Atomic-scale Design Approach;Journal of the Japan Society for Precision Engineering;2014
5. Step and Terrace Formation on Ge(111) Surface in H$_{2}$ Annealing;Applied Physics Express;2012-11-20
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