Effects of high temperature annealing on the atomic layer deposited HfO2/β-Ga2O3 (010) interface
Author:
Affiliation:
1. Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122, USA
2. Department of Electrical and Computer Engineering, University of Delaware, Newark, Delaware 19716, USA
Funder
National Science Foundation
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
https://aip.scitation.org/doi/am-pdf/10.1063/5.0070105
Reference33 articles.
1. Gallium Oxide
2. Enhancement-Mode Ga2O3 Vertical Transistors With Breakdown Voltage >1 kV
3. Z. Hu, K. Nomoto, W. Li, R. Jinno, T. Nakamura, D. Jena, and H. Xing, “1.6 kV vertical Ga2O3 FinFETs with source-connected field plates and normally-off operation,” in 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), Shanghai, China (IEEE, 2019), pp. 483–486.
4. Interface trapping in (2¯01) β-Ga2O3 MOS capacitors with deposited dielectrics
5. Al2O3/ $\beta $ -Ga2O3(-201) Interface Improvement Through Piranha Pretreatment and Postdeposition Annealing
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