1. K. Mistry et al., “A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging,” in 2007 International Electron Devices Meeting, San Francisco, CA (IEEE, 2007), pp. 247–250.
2. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, in Technical Digest 2007 Symposium on VLSI Technology (IEEE, 2003), p. 9.
3. E. Cartier, V. Narayanan, E. P. Gusev, P. Jamison, B. Linder, M. Steen, K. K. Chan, M. Frank, N. Bojarczuk, M. Copel, S. A. Cohen, A. Callegari, S. Zafar, M. Gribelyuk, M. Chudzik, C. Cabral, Jr., R. A. Carruthers, C. D'Emic, J. Newbury, D. Lacey, S. Guha, and R. Jammy, in Technical Digest 2004 Symposium on VLSI Technology (IEEE, 2004), p. 44.
4. V. Narayanan, V. K. Paruchuri, N. A. Bojarczuk, B. P. Linder, B. Doris, Y. H. Kim, S. Zafar, J. Stathis, M. Copel, E. Cartier, A. Callegari, S. Guha, G. Shahidi, and T. C. Chen, in Technical Digest 2006 VLSI Symposium on VLSI Technology (IEEE, 2006), p. 178.
5. Examination of flatband and threshold voltage tuning of HfO2∕TiN field effect transistors by dielectric cap layers