Analysis of PMOS logic two tail comparator for less power consumption compared with CMOS comparator

Author:

Gajawada Varun Sai,Mohana J.

Publisher

AIP Publishing

Reference24 articles.

1. Babayan-Mashhadi, Samaneh. n.d. “Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator.” Accessed April 8, 2021. https://xilirprojects.com/wp-content/uploads/2019/05/Analysis-and-Design-of-a-Low-Voltage-Low-Power-Double-Tail-Comparator.pdf.

2. Balayan Sapna, Gupta Anshu. n.d. “Low Power and Low Voltage Double Tail Dynamic Latch Comparator Using 180nm Technology.” Accessed April 8, 2021. https://ijaers.com/uploads/issue_files/17%20IJAERS-MAR-2017-72-Low%20Power%20and%20Low%20Voltage%20Double%20Tail%20Dynamic%20Latch%20Comparator%20using%20180nm%20Technology.pdf.

3. High-speed, low-power BiCMOS comparator using a pMOS variable load

4. Notice of Violation of IEEE Publication Principles: Design of efficient double tail comparator for low power

5. Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage

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