Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-019-01518-7.pdf
Reference28 articles.
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2. Zhu, Z., Liu, M., Wang, Q., & Yang, Y. (2014). A single-channel 8-bit 660MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS. Microelectronics Journal, 45(7), 880–885.
3. Ragab, K., Chen, L., Sanyal, A., & Sun, N. (2015). Digital background calibration for pipelined ADCs based on comparator decision time quantization. IEEE Transactions on Circuits and Systems II: Express Briefs, 62(5), 456–460.
4. Yang, B.-D. (2014). 250-mV supply subthreshold CMOS voltage reference using a low-voltage comparator and a charge-pump circuit. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(11), 850–854.
5. Yamamoto, K., & Carusone, A. (2012). A 1-1-1-1 MASH delta-sigma modulator with dynamic comparator-based OTAs. IEEE Journal of Solid-State Circuits, 47(8), 1866–1883.
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