Characterization and modeling of SET/RESET cycling induced read-disturb failure time degradation in a resistive switching memory
Author:
Affiliation:
1. Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan
Funder
Ministry of Science and Technology, Taiwan
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
http://aip.scitation.org/doi/pdf/10.1063/1.5009042
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