Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface
Author:
Affiliation:
1. Keio University
Publisher
IJNC Editorial Committee
Link
https://www.jstage.jst.go.jp/article/ijnc/8/1/8_124/_pdf
Reference3 articles.
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2. [18] M.Arifuzzaman and O.A.Dobre and M.H.Ahmed and T.M.N.Ngatched. Joint ROuting and MAC Layer QoS-Aware Protocol for Wireless Sensor Networks. IEEE Global Communications Conference (GLOBECOM), 2016.
3. [19] H. Jin, M. Frumkin, and J. Yan. The OpenMP Implementation of NAS Parallel Benchmarks and Its Performane. In NAS Technical Report NAS-99-011, October 1999.
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