TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface
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Published:2023-08-04
Issue:3
Volume:13
Page:48
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ISSN:2079-9268
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Container-title:Journal of Low Power Electronics and Applications
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language:en
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Short-container-title:JLPEA
Author:
Kayashima Hideto1, Amano Hideharu1
Affiliation:
1. Department of Open Environment Science, Graduate School of Science and Technology, Keio University, Tokyo 223-8522, Japan
Abstract
The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.
Funder
JSPS Kakenhi JST CREST
Subject
Electrical and Electronic Engineering
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