High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

Author:

Darji Anand D,Kushwah Shailendra Singh,Merchant Shabbir N,Chandorkar Arun N

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Information Systems,Signal Processing

Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Improved DWT and IDWT architectures for image compression;Microprocessors and Microsystems;2024-02

2. A signal denoising system for CCD spectrometer based on FPGA;Fourth International Conference on Signal Processing and Computer Science (SPCS 2023);2023-12-21

3. Digital Image Decoder for Efficient Hardware Implementation;Sensors;2022-12-01

4. Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2-D Forward Discrete Wavelet Transform;Microprocessors and Microsystems;2021-11

5. Memory-efficient architecture for FrWF-based DWT of high-resolution images for IoMT applications;Multimedia Tools and Applications;2021-01-05

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