An optimised twin precision multiplier for ASIC environment

Author:

Asirvatham Rosi,Ramachandran Seshasayanan

Publisher

Springer Science and Business Media LLC

Reference20 articles.

1. M Själander, H Eriksson, P Larsson-Edefors, An efficient twin- precision multiplier, in Proc. 22nd IEEE Int. Conf. Comput. Des, 2004, pp. 30–33

2. M Själander, P Larsson-Edefors, Multiplication Acceleration Through Twin Precision, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, 9th edn., 2009

3. Differences between FPGA and ASIC. http://www.xilinx.com/fpga/asic.htm .

4. About ASIC and FPGA. http://www.altera.com

5. GH Loh, Exploiting data-width locality to increase superscalar execution bandwidth, in Proc. 35th Int. Symp. Microarchitecture, 2002, pp. 395–405

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