Hardware Reduction for Lut–Based Mealy FSMs-Reference-Cited by-同舟云学术

Hardware Reduction for Lut–Based Mealy FSMs

Published:2018-09-01 Issue:3 Volume:28 Page:595-607
ISSN:2083-8492
Container-title:International Journal of Applied Mathematics and Computer Science
language:en
Short-container-title:

Author:

Barkalov Alexander¹,Titarenko Larysa¹,Mielcarek Kamil¹

Affiliation:

1. Institute of Metrology, Electronics and Computer Science University of Zielona Góra, ul. prof. Z. Szafrana 2, Zielona Góra , Poland

Abstract

Abstract A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

Publisher

Walter de Gruyter GmbH

Subject

Applied Mathematics,Engineering (miscellaneous),Computer Science (miscellaneous)

Link

https://www.sciendo.com/pdf/10.2478/amcs-2018-0046

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