A New Model of Dynamic Logic Circuit with NMOS based Keeper-Reference-Cited by-同舟云学术

A New Model of Dynamic Logic Circuit with NMOS based Keeper

Published:2020-12-01 Issue:1 Volume:12 Page:1-14
ISSN:2066-8910
Container-title:Acta Universitatis Sapientiae, Electrical and Mechanical Engineering
language:en
Short-container-title:

Author:

Islam Riazul¹,Biswas Satyendra N.²

Affiliation:

1. Department of Electrical and Electronic Engineering , International Islamic University Chittagong , Chittagong , Bangladesh ., iriazul74@gmail.com

2. Department of Electrical and Electronic Engineering , Ahsanullah University of Science and Technology , Dhaka , Bangladesh , sbiswas.eee@auct.edu

Abstract

Abstract Dynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit.

Publisher

Walter de Gruyter GmbH

Link

https://www.sciendo.com/pdf/10.2478/auseme-2020-0001

Reference16 articles.

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