Author:
Ansari M. Adil,Kim Dooyoung,Jung Jihun,Park Sungju
Publisher
The Institute of Electronics Engineers of Korea
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Refresh Triggered Computation;ACM Transactions on Architecture and Code Optimization;2021-01-21
2. ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC;Journal of Low Power Electronics and Applications;2019-06-17
3. A Novel Hybrid Test Architecture for Router Testing of 2D-Mesh NoC;2019 27th Iranian Conference on Electrical Engineering (ICEE);2019-04
4. Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2017-12-24
5. Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks;Journal of Electronic Testing;2016-01-20