Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-016-5565-5.pdf
Reference42 articles.
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3. Aktouf C (2002) A complete strategy for testing an on-chip multiprocessor architecture. IEEE Des Test Comput 19:18–28
4. Amory A, Goossens K, Marinissen EJ, Lubaszewski M, Moraes F (2007) Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. IET Comput Digit Tech 1:197–206
5. Amory AM, Lazzari C, Lubaszewski MS, Moraes FG (2011) A new test scheduling algorithm based on networks-on-chip as test access mechanisms. J Parallel Distrib Comput 71:675–686
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1. Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks;Journal of Electronic Testing;2020-04-27
2. ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC;Journal of Low Power Electronics and Applications;2019-06-17
3. Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2017-12-24
4. A Multi-Verse Optimizer with Levy Flights for Numerical Optimization and Its Application in Test Scheduling for Network-on-Chip;PLOS ONE;2016-12-07
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