1. J. Mitard , L.Witters , Y.Sasaki , H.Arimura , A.Schulze , R.Loo , L.-A.Ragnarsson , A.Hikavyy , D.Cott , T.Chiarella , S.Kubicek , H.Mertens , R.Ritzenthaler , C.Vrancken , P.Favia , H.Bender , N.Horiguchi , K.Barla , D.Mocuta , A.Mocuta , N.Collaert and A.-Y.Thean , A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs , IEEE , 2016 , pp. 1–2 , DOI: 10.1109/VLSIT.2016.7573368
2. Processing Technologies for Advanced Ge Devices
3. Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials
4. Heteroepitaxy and selective area heteroepitaxy for silicon photonics
5. Site Selective Integration of III–V Materials on Si for Nanoscale Logic and Photonic Devices