Inverted process for graphene integrated circuits fabrication
Author:
Affiliation:
1. Institute of Microelectronics
2. Tsinghua University
3. Beijing, China
4. Chinese Academy of Sciences
Abstract
CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors and monolithic graphene ICs.
Funder
National Natural Science Foundation of China
Publisher
Royal Society of Chemistry (RSC)
Subject
General Materials Science
Link
http://pubs.rsc.org/en/content/articlepdf/2014/NR/C3NR06904D
Reference23 articles.
1. High-frequency self-aligned graphene transistors with transferred gate stacks
2. Graphene Ambipolar Multiplier Phase Detector
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