Van der Waals negative capacitance transistors

Author:

Wang Xiaowei,Yu Peng,Lei Zhendong,Zhu ChaoORCID,Cao XunORCID,Liu Fucai,You LuORCID,Zeng Qingsheng,Deng Ya,Zhu ChaoORCID,Zhou Jiadong,Fu Qundong,Wang JunlingORCID,Huang Yizhong,Liu ZhengORCID

Funder

National Research Foundation Singapore

A*STAR | Institute of Materials Research and Engineering

Publisher

Springer Science and Business Media LLC

Subject

General Physics and Astronomy,General Biochemistry, Genetics and Molecular Biology,General Chemistry

Reference37 articles.

1. Taur, Y. & Ning, T. H. Fundamentals of Modern VLSI Devices. (Cambridge University Press, New York, USA, 1998).

2. Chandrakasan, A. P. & Brodersen, R. W. Minimizing power-consumption in digital Cmos circuits. Proc. IEEE 83, 498–523 (1995).

3. Salahuddin, S. & Dattat, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–410 (2008).

4. Zhirnov, V. V. & Cavin, R. K. Negative capacitance to the rescue? Nat. Nanotech. 3, 77–78 (2008).

5. Kobayashi, M. & Hiramoto, T. Device design guideline for steep slope ferroelectric FET using negative capacitance in sub-0.2V operation: operation speed, material requirement and energy efficiency. VLSI Tech. Symp, 212–213 (2015).

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