Author:
Kazemi Arman,Müller Franz,Sharifi Mohammad Mehdi,Errahmouni Hamza,Gerlach Gerald,Kämpfe Thomas,Imani Mohsen,Hu Xiaobo Sharon,Niemier Michael
Abstract
AbstractHyperdimensional computing (HDC) is a brain-inspired computational framework that relies on long hypervectors (HVs) for learning. In HDC, computational operations consist of simple manipulations of hypervectors and can be incredibly memory-intensive. In-memory computing (IMC) can greatly improve the efficiency of HDC by reducing data movement in the system. Most existing IMC implementations of HDC are limited to binary precision which inhibits the ability to match software-equivalent accuracies. Moreover, memory arrays used in IMC are restricted in size and cannot immediately support the direct associative search of large binary HVs (a ubiquitous operation, often over 10,000+ dimensions) required to achieve acceptable accuracies. We present a multi-bit IMC system for HDC using ferroelectric field-effect transistors (FeFETs) that simultaneously achieves software-equivalent-accuracies, reduces the dimensionality of the HDC system, and improves energy consumption by 826x and latency by 30x when compared to a GPU baseline. Furthermore, for the first time, we experimentally demonstrate multi-bit, array-level content-addressable memory (CAM) operations with FeFETs. We also present a scalable and efficient architecture based on CAMs which supports the associative search of large HVs. Furthermore, we study the effects of device, circuit, and architectural-level non-idealities on application-level accuracy with HDC.
Funder
Semiconductor Research Corporation
ECSEL Joint Undertaking project TEMPO in collaboration with the European Union’s H2020 Framework Program and National Authorities
National Science Foundation, United States
Office of Naval Research,United States
Air Force Office of Scientific Research
Publisher
Springer Science and Business Media LLC
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